This application relies for priority upon Korean Patent Application No. 99-48926, filed on Nov. 5, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device and a method for fabricating such a device. More particularly, the present invention relates to a DRAM cell and a method for fabricating such a DRAM.
Semiconductor memories are considered one of the crucial microelectronics components for mainframe computers, PCs, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memory devices can be characterized as either volatile random access memory devices (RAMs) or non-volatile memory devices (NVMs). RAMs can further include dynamic RAMs (DRAMs) and static RAMs (SRAMs). As is well known, DRAMs have about four times as high a degree of integration compared to SRAMs. Because of this, DRAMs have been widely used in computer main memories.
DRAMs are composed of a cell array region that has a plurality of memory cell arrays, and a peripheral circuit region that controls and drives the memory cell arrays. Each memory cell typically consists of a cell storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the cell capacitor. The properties of the cell storage capacitor directly affects the characteristics of the DRAM, such as data retention, soft error rate, low voltage performance, or the like. In particular, a higher capacitance of the cell capacitor improves the data retention characteristics and low voltage characteristics, and reduces the soft error rate of the DRAM. Accordingly, in order to realize high density DRAM devices, the cell capacitor is formed to have an acceptable level of capacitance in a given cell.
U.S. Pat. No. 5,597,756 by Fazan et al entitled as xe2x80x9cPROCESS FOR FABRICATING A CUP-SHAPED DRAM CAPACITOR USING A MULTI-LAYER PARTIALLY-SACRIFICIAL STACKxe2x80x9d, the disclosure of which is incorporated herein by ,  greater than reference, discloses a capacitor storage node having an HSG silicon layer on its surface. Also, U.S. Pat. No. 5,907,772 by Iwazaki entitled as xe2x80x9cMETHOD FOR PRODUCING CYLINDRICAL STORAGE NODE OF STACKED CAPACITOR IN MEMORY CELLxe2x80x9d, the disclosure of which is incorporated herein by reference, discloses a planarized interlayer insulating layer formed on a semiconductor substrate. The semiconductor substrate has an access transistor and a cylindrical storage node formed on the planarized interlayer insulating layer, which is electrically connected to a source region of the access transistor.
FIGS. 1 to 5 are cross-sectional views of a conventional semiconductor substrate, at selected stages of a DRAM fabrication process. Referring to FIG. 1, a device isolation region 23 is formed in a predetermined region of a semiconductor substrate 21 to define an active region. A gate oxide layer 25 is formed on the active region. Doped polysilicon and a silicon nitride layers are sequentially formed on the resulting structure. The doped polysilicon and the silicon nitride layers are patterned to form a first and a second gate patterns 30a and 30b, intersecting the active region and neighbouring each other. The first gate pattern 30a comprises a stacked layer of a first polysilicon pattern 27a and a first silicon nitride layer pattern 29a. Similarly, the second gate pattern 30b comprises a stacked layer of a second polysilicon pattern 27b and a second silicon nitride layer pattern 29b. The first and second polysilicon patterns 27a and 27b respectively serve as a gate electrode of neighbouring access transistors.
A silicon nitride layer is formed on the entire surface of the semiconductor substrate 21 having the first and second gate patterns 30a and 30b and is then anisotropically etched to form a side wall spacer 31 on side walls of the first and second gate patterns 30a and 30b. 
Referring now to FIG. 2, an insulating layer 33, such as a CVD oxide layer, is formed on the resulting structure. Selected portions of the insulating layer 33 are then etched to form pad contact holes that respectively expose the active regions outside of the first and second gate patterns 30a and 30b. A contact hole, defined between the first and second gate patterns 30a and 30b, is a bit line pad contact hole. Contact holes outside of the bit line pad contact hole are respectively first and second storage node pad contact holes, respectively. A bit line pad 35d and first and second storage node pads 35a and 35b are formed by respectively filling the bit line pad contact hole and the first and second storage node pad contact holes with a conductive material.
Referring now to FIG. 3, a first interlayer insulating layer 37, such as a CVD oxide, is formed on the resulting structure. A selected portion of the first interlayer insulating layer 37 is then etched to form a bit line contact hole (not shown), which exposes the bit line pad 35d. The bit line contact hole is then filled with a conductive material to form a bit line (not shown). A second interlayer insulating layer 39, an etching stopper layer 41, and a sacrificial insulating layer 43 are then sequentially formed on the first interlayer insulating layer 37 including the bit line. The second interlayer insulating layer 39 comprises a CVD oxide layer planarized by CMP process. The etching stopper layer 41 comprises a material having an etching selectivity with respect to an oxide, such as a silicon nitride layer. The sacrificial insulating layer 43 comprises a CVD oxide.
Referring now to FIG. 4, the sacrificial insulating layer 43, the etching stopper layer 41, the second interlayer insulating layer 39, and the first interlayer insulating layer 37 are sequentially patterned to form first and second storage node holes 45a and 45b, respectively exposing the first and second storage node pads 35a and 35b. At this time, the first and second storage nodes holes 45a and 45b can be misaligned to the storage node pads 35a and 35b, thereby exposing the bit line pad 35d, as shown in FIG. 4.
A conformal conductive layer is deposited on the sacrificial insulating layer 43 and in the holes 45a and 45b to form first and second cylindrical storage nodes 47a and 47b. As noted above, in the case of a misalignment of the first and second storage node holes 45a and 45b, one of the first and second storage nodes 47a and 47b, for example, the second storage node 47b, becomes electrically connected to the bit line pad 35d. 
Referring to FIG. 5, the sacrificial insulating layer 43 is etched to expose outer sidewalls of the first and second cylindrical storage nodes 47a and 47b. The etching stopper layer 41 serves as an end-point of the etching and thus the second interlayer insulating layer 39 is not exposed.
As described above, when misalignment occurs during a photolithography process for forming storage node holes, the storage node and the bit line pad may be electrically connected, causing a malfunction of the fabricated DRAMs.
The present invention was made in view of above-mentioned problems and it is an object of the present invention to provide a method of fabricating a DRAM cell that can prevent bit line pad from being exposed by the storage node hole even when there is misalignment of the storage node hole during a photolithography process.
It is another object of the present invention to provide a method of fabricating a high performance cell capacitor compatible with high density DRAMs.
It is still another object of the present invention to provide a DRAM cell in which the storage node and the bit line pad are electrically separated even when there is misalignment of the storage node hole to the bit line.
In accordance with the present invention, a method is provided for fabricating a cylindrical capacitor. The method includes forming first and second access transistors that share a common drain region over a semiconductor substrate. A first interlayer insulating layer is formed on the semiconductor substrate and the first and second access transistors. A protection layer pattern is provided that completely covers the common drain region on the first interlayer insulating layer. An insulator is formed over the first interlayer insulating layer and the protection layer pattern. The insulator includes a second interlayer insulating layer. The insulator and the first interlayer insulating layer are sequentially patterned to form first and second storage node holes, respectively exposing a first source region of the first access transistor and a second source region of the second access transistor. First and second storage nodes are formed in the first and second storage node holes, respectively.
The forming of the first and the second access transistors may be performed by forming a device isolation layer over a selected portion of the semiconductor substrate to define a primary active region; forming first and second insulated gate patterns crossing over the primary active region to divide the primary active region into first and third active regions; forming sidewall spacers on sidewalls of the first and second gate patterns; and forming the common drain region at the first active region between the first and second gate patterns, and the first and the second source regions at the second and third active regions next to the first and second insulated gate patterns, respectively.
The method for fabricating a DRAM cell may further include forming a bit line pattern between the protection layer pattern and the common drain region.
The forming of the protection layer pattern may be performed by forming the protection layer over the first interlayer insulating layer and over the bit line pattern; forming a photoresist pattern over the protection layer to cover the common drain region and expose the first and second source regions; and anisotropically etching the protection layer using the photoresist pattern as an etching mask to form the protection layer pattern completely covering bit line pattern over the common drain region, while concurrently forrning sidewall spacers on sidewalls of the bit line pattern exposed by the protection layer pattern.
The method for fabricating a DRAM cell may further include forming a first storage node pad interposed between the first storage node and the first source region of the first access transistor; forming a second storage node pad interposed between the second storage node and the second source region of the second access transistor; and forming a bit line pad interposed between the bit line pattern and the common drain region.
The forming of the insulator may include forming the second interlayer insulating layer over the first interlayer insulating layer and the protection pattern; forming an etching stopper layer over the second interlayer insulating layer; and forming a sacrificial insulating layer over the etching stopper layer.
The first interlayer insulating layer, the second interlayer insulating layer, and the sacrificial insulating layer preferably comprise silicon oxide. The protection layer and the etching stopper layer preferably comprise silicon nitride.
The forming of the first and second storage nodes may be performed by forming a conformal conductive layer over the sacrificial insulating layer and in the first and second storage node holes; forming a planarized insulator filling the first and second storage node holes over the conformal conductive layer; and blanket etching the planarized insulator and the conformal conductive layer until a top surface of the sacrificial insulating layer is exposed.
The method for fabricating a DRAM cell may include removing the exposed sacrificial insulating layer and the remainder of the planarized insulator in the first and second storage node holes, to expose outer and inner sidewalls of each of the first and second storage node, respectively; forming a dielectric layer over the etching stopper layer and the storage nodes; and forming a plate electrode layer over the dielectric layer.
To achieve these objectives and in accordance with the present invention, a DRAM cell is provided. The DRAM cell includes first and second access transistors formed over a semiconductor substrate, the first and second access transistors sharing a common drain region and having first and second source regions, respectively; first and second storage nodes electrically connected to the first and second source regions, respectively; and a protection layer pattern disposed between the common drain region and the first and second storage nodes, the protection layer pattern completely covering the common drain region.
The DRAM cell may further include a bit line pad formed over the common drain region; a first storage node pad formed over the first source region; and a second storage node pad formed over the second source region. The first and second storage nodes are electrically connected to the first and second source regions, respectively. Also, the bit line pad is electrically connected to the common drain region.
The DRAM cell may further include a bit line pattern disposed between the bit line pad and the protection layer pattern, the bit line pattern being electrically connected to the bit line pad.
The protection layer pattern may be extended to cover not only a part of the bit line pattern over the common drain region, but also a part of the first and second gate patterns of the first and second access transistors adjacent to the common drain region.
The DRAM cell may further include a first interlayer insulating layer disposed between the protection layer pattern and the first and second gate patterns of the first and second access transistors, respectively.
The protection layer pattern preferably has an etching selectivity with respect to the first interlayer insulating layer. The first interlayer insulating layer preferably comprises silicon oxide and the protection layer pattern preferably comprises silicon nitride.
As described above, in accordance with the present invention, the common drain region, the bit line pad or bit line pattern are not exposed by the storage nodes hole because of the presence of a protection layer pattern that has an etching selectivity with respect to the first and second interlayer insulating layers.